The present invention relates to a method and/or architecture for input threshold circuits generally and, more particularly, to a method and/or architecture for a self-calibrating, zero power precision input threshold circuit.
Input signals are presented to electronic circuits for control and communication purposes. The input signals may contain noise. The electronic circuits need to ignore changes in the input signal voltage levels that are caused by the noise. Electronic circuits include input circuits to differentiate between input is signal changes and noise. The input circuits differentiate input signal changes from noise using an input threshold voltage. When the input signal levels are above the input threshold voltage, the input circuit can present a first logic state (i.e., a logic LOW). When the input signals are below the input threshold voltage, the input circuit can present a second logic state (i.e., a logic HIGH). When a precise threshold is not required, a simple CMOS logic gate buffer is used for each input circuit. If precision thresholds are desired, the input circuits use a voltage comparator and a precision voltage reference.
Referring to FIG. 1, a schematic diagram of a circuit 10 illustrating a conventional CMOS input circuit is shown. The circuit 10 has a PMOS transistor 12 and a NMOS transistor 14. The input threshold voltage of the circuit 10 is determined by the threshold voltages (i.e., Vth) of the transistors 12 and 14. When an input signal IN has a voltage level below the threshold of the transistors 12 and 14, the transistor 12 conducts pulling the output signal OUT to a logic HIGH. When the signal IN has a level that is above the threshold of the transistors 12 and 14, the transistor 14 conducts pulling the signal OUT to a logic LOW. The input circuit 10 has a disadvantage of inherently imprecise threshold voltage control. The input threshold is dominated by process variation. Process variation can result in each CMOS input circuit of an integrated circuit having a different input threshold voltage level. Different input threshold voltage levels can cause inconsistent operation from input to input and chip to chip. The transistors of an integrated circuit (IC) can be tightly matched. Therefore, the variation between inputs on one chip can be much less than the chip to chip variation.
Referring to FIG. 2, a block diagram of a circuit 20 illustrating a conventional input circuit with a precise input threshold is shown. The circuit 20 has a voltage comparator 22 and a precision voltage reference circuit 24. When the signal IN has a voltage level that is greater than a level presented by the precision voltage reference 24, the comparator 22 presents the signal OUT in the first state (i.e., a logic LOW). When the signal IN has a voltage level that is lower than the level presented by the precision voltage reference 24, the comparator 22 presents the signal OUT in the second state (i.e., a logic HIGH). Disadvantages of the circuit 20 include: consuming DC power, requiring the precision voltage reference, and using a significant amount of area. The area penalty occurs for each input that is independently monitored.
The input circuit can require hysteresis for greater noise immunity. When the input circuit has hysteresis, the input signal must be above a first threshold (i.e., a high threshold) to be recognized as a logic HIGH and below a second threshold (i.e., a low threshold) to be recognized as a logic LOW. An input circuit with hysteresis that requires precise thresholds can require two precision voltage references and two voltage comparators, doubling the DC power consumption and area penalty.
An input circuit with a precise threshold voltage that could be implemented without using circuits that consume DC power and/or requiring a large area would be desirable.
The present invention concerns an apparatus comprising one or more input circuits. The input circuits may have minimal DC power consumption and may be configured to generate an output signal in response to an input signal and an input threshold. The input threshold may be adjusted in response to a control signal.
The objects, features and advantages of the present invention include a method and/or architecture for a self-calibrating, zero power precision input threshold circuit that may provide (i) a precise input threshold voltage, (ii) no standby power consumption after calibration is completed, (iii) self-calibrating input circuits, (iv) efficient area implementation of precision threshold input circuits, (v) tight thresholds over many inputs without multiplexing, (vi) user initiated re-calibration, (vii) a threshold set to either an absolute value or a percentage of supply voltage level, (ix) no additional external components required, and/or (x) an input circuit that may be calibrated during or after the manufacturing process.